Communications systems can be divided into two types, packet switched or circuit switched. A circuit switched network provides for a dedicated physical path or channel established between two end points or terminals on the network for the duration of the connection. The channel can be dedicated wiring or a portion of the spectrum in wireless communications. Even if no actual communication is taking place over a dedicated circuit, that circuitry still remains unavailable to other users. In contrast, packet switched networks allow the same data path to be shared among many users in the network, by breaking communication down into relatively small units of data called packets, which are routed through a network based on a destination address contained within each packet. This results in increased bandwidth availability.
A packet, also known in the art as a frame of information, generally comprises a preamble part and a data part. The preamble may have a number of synchronization symbols, used for achieving synchronization. The words packet and frame will be interchangeably used throughout this document.
In serial data transmission, synchronization processes ensure that a receiving end recognizes symbols in the order in which the transmitting end has sent them, and can determine where one symbol ends and the next begins. Synchronization processes include clock synchronization, symbol synchronization when the symbol rate is different than the clock rate, frame synchronization when a frame contains several symbols, and all rely on clocking mechanisms to synchronize the signals between the sending and receiving machines. Synchronization can also refer to other aspects of a data signal in connection with the ability of a terminal to interpret this data signal, such as frequency, amplitude, phase, etc.
Typically, for a circuit switched network, clock synchronization and symbol synchronization are generally determined at the configuration of the circuit and maintained for the duration of the connection. However, in general, for packet switched networks there are no dedicated paths, and packets may arrive at a receiving end from any other terminal at any given reference point, with respect to an internal reference system of the receiving end. Specifically, interpretation of a received packet with respect to an internal timing reference system of the receiving end is currently a complex aspect to tackle. The arrival time of packets is generally not known at the receiving end prior to the arrival of the packet, especially at a timing resolution less than the duration of a symbol used for signaling. Therefore, clock and symbol synchronization for packet switched networks are generally more complex and/or less accurate than in the circuit switched networks. Multiple access systems such as Time Division Multiple Access (TDMA) where the network is generally shared and there is typically an unknown time delay between terminals, or wireless networks with channel fading conditions or communications over power line channels where a light has been switched on, present especially difficult challenges in achieving synchronization.
Since packets generally arrive at the receiving end at unknown times with respect to an internal reference timing system, traditionally, in packet switched network, frame synchronization is performed for every incoming frame of information at a receiver terminal. A correlation receiver may be used, for example, to detect sync symbols within the preamble of incoming packets, in order to detect packets. Decoding of the actual data, within packets, would follow the detection of the preamble. This approach presents several drawbacks: firstly, preamble detection and alignment of sync symbols with an internal clock involves complex computations, therefore requiring such computations for every incoming packet results in more complex hardware requirements. Secondly, the sync symbols detection and the decoding of the data part are carried within a single frame, for each frame, which can lead to either accuracy issues for frames with a preamble of a shorter duration, or to timing and bandwidth constraints when a longer duration preamble is used.
MIL-STD-1553 or simply 1553, is an approximately 30 year old technology that defines the electrical and signaling characteristics for 1 Mbps communications over an asynchronous serial, command/response digital data bus on which messages are time division multiplexed among users. The transmission medium is a twisted wire cable pair. 1553 specifies all of the electrical characteristics of the receivers, transmitters, and cable used to implement the bus, as well as the complete message transmission protocol. 1553 is designed for high integrity message exchanges between unattended equipment. According to the preferred embodiment disclosed in the co-assigned U.S. patent application Ser. No. 11/419,742, which is incorporated here by reference, Orthogonal Frequency Division Multiplexing (OFDM), closely related to Discrete Multi-Tone (DMT), is used to better utilize the available bandwidth on the bus, creating an “overlay” packet-switched network to operate concurrently and without disturbing existing 1553 communications.